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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
4-Bit Binary Counter
The MC10H016 is a high-speed synchronous, presettable, cascadable 4-bit binary counter. It is useful for a large number of conversion, counting and digital integration applications. * Counting Frequency, 200 MHz Minimum * Improved Noise Margin 150 mV (Over Operating Voltage and Temperature Range) * Voltage Compensated * MECL 10K-Compatible * Positive Edge Triggered MAXIMUM RATINGS
Characteristic Power Supply (VCC = 0) Input Voltage (VCC = 0) Output Current -- Continuous -- Surge Operating Temperature Range Storage Temperature Range -- Plastic -- Ceramic Symbol VEE VI Iout TA Tstg Rating -8.0 to 0 0 to VEE 50 100 0 to +75 -55 to +150 -55 to +165 Unit Vdc Vdc mA C C
MC10H016
L SUFFIX CERAMIC PACKAGE CASE 620-10 P SUFFIX PLASTIC PACKAGE CASE 648-08 FN SUFFIX PLCC CASE 775-02
ELECTRICAL CHARACTERISTICS (VEE = -5.2 V 5%) (See Note)
0 Characteristic Power Supply Current Input Current High All Except MR Pin 12 MR Input Current Low High Output Voltage Low Output Voltage High Input Voltage Low Input Voltage Symbol IE IinH -- -- IinL VOH VOL VIH VIL 0.5 -1.02 -1.95 -1.17 -1.95 450 1190 -- -0.84 -1.63 -0.84 -1.48 -- -- 0.5 -0.98 -1.95 -1.13 -1.95 265 700 -- -0.81 -1.63 -0.81 -1.48 -- -- 0.3 -0.92 -1.95 -1.07 -1.95 265 700 -- -0.735 -1.60 -0.735 -1.45 A Vdc Vdc Vdc Vdc Min -- Max 126 Min -- 25 Max 115 Min -- 75 Max 126 Unit mA A
DIP PIN ASSIGNMENT
VCC1 Q1 Q0 TC PE CE PO VEE 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC2 Q2 Q3 CP MR P3 P2 P1
AC PARAMETERS
Propagation Delay Clock to Q Clock to TC MR to Q Set-up Time Pn to Clock CE or PE to Clock Hold Time Clock to Pn Clock to CE or PE Counting Frequency Rise Time Fall Time tpd 1.0 0.7 0.7 tset 2.0 2.5 thold 1.0 0.5 fcount tr tf 200 0.5 0.5 -- -- -- 2.0 2.0 1.0 0.5 200 0.5 0.5 -- -- -- 2.1 2.1 1.0 0.5 200 0.5 0.5 -- -- -- 2.2 2.2 MHz ns ns -- -- 2.0 2.5 -- -- 2.0 2.5 -- -- ns CE L H L H X X 2.4 2.4 2.4 1.0 0.7 0.7 2.5 2.5 2.5 1.0 0.7 0.7 2.7 2.6 2.6 ns ns
Pin assignment is for Dual-in-Line Package. For PLCC pin assignment, see the Pin Conversion Tables on page 6-11 of the Motorola MECL Data Book (DL122/D).
TRUTH TABLE
PE L L H H X X MR L L L L L H CP Z Z Z Z ZZ X Function Load Parallel (Pn to Qn) Load Parallel (Pn to Qn) Count Hold Masters Respond; Slaves Hold Reset (Qn = LOW, TC = HIGH)
NOTE: Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 Ifpm is maintained. Outputs are terminated through a 50-ohm resistor to -2.0 volts.
Z = Clock Pulse (Low to High); ZZ = Clock Pulse (High to Low) Features include assertion inputs and outputs on each of the four master/slave counting flip-flops. Terminal count is generated internally in a manner that allows synchronous loading at nearly the speed of the basic counter.
9/96
(c) Motorola, Inc. 1996
2-1
REV 6
4-Bit Binary Counter Logic Diagram
MC10H016
MOTOROLA
Q0 Q P1 P2 P3
SLAVE MASTER
PE
Q1 Q
SLAVE MASTER
Q2 Q
SLAVE
Q3
MASTER
P0 Q Q Q
MR
Q
Q
Q
Q
CE
CP
TC
Note that this diagram is provided for understanding of logic operation only. It should not be used for evaluation of propagation delays as many gate functions are achieved internally without incurring a full gate delay.
2-2 Q0-Q3
CE MR Tc C MR Tc PE CE PE
1/2 10H109
Q0-Q3
Q0-Q3
CE
Q0-Q3
PE MR Tc C CE
Q0-Q3
FO PE
CE
PE
LSB
MR
MSB
MR
C C
Tc
C
Tc
P0-P3 P0-P3
P0-P3 1/2 10H109 1/2 10H109
P0-P3 1/2 10H109
P0-P3
CLOCK
/N Counter 1 to 16 5 MC10H016 Cascaded for 5 Stage Presettable Counter
Max freq. is only OR gate delay below max when counting alone.
MECL Data DL122 -- Rev 6
MC10H016
OUTLINE DIMENSIONS
FN SUFFIX PLASTIC PLCC PACKAGE CASE 775-02 ISSUE C
B -N- Y BRK D -L- -M- W D Z
0.007 (0.180) M T L-M U
S
N
S S
0.007 (0.180) M T L-M
N
S
20
1
X V VIEW D-D
G1
0.010 (0.250)
S
T L-M
S
N
S
A Z R
0.007 (0.180) M T L-M 0.007 (0.180) M T L-M
S
N N
S
S
S
H
0.007 (0.180) M T L-M
S
N
S
C
E 0.004 (0.100) G G1 0.010 (0.250) S T L-M J -T-
SEATING PLANE
K1 K F VIEW S 0.007 (0.180)
M
VIEW S
S
T L-M
S
N
S
N
S
NOTES: 1. DATUMS -L-, -M-, AND -N- DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM -T-, SEATING PLANE. 3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635).
DIM A B C E F G H J K R U V W X Y Z G1 K1
INCHES MIN MAX 0.385 0.395 0.385 0.395 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 --- 0.025 --- 0.350 0.356 0.350 0.356 0.042 0.048 0.042 0.048 0.042 0.056 --- 0.020 2_ 10 _ 0.310 0.330 0.040 ---
MILLIMETERS MIN MAX 9.78 10.03 9.78 10.03 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 --- 0.64 --- 8.89 9.04 8.89 9.04 1.07 1.21 1.07 1.21 1.07 1.42 --- 0.50 2_ 10 _ 7.88 8.38 1.02 ---
MECL Data DL122 -- Rev 6
2-3
MOTOROLA
MC10H016
OUTLINE DIMENSIONS
L SUFFIX CERAMIC DIP PACKAGE CASE 620-10 ISSUE V
9
-A-
16
-B-
1 8
C
L
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. DIM A B C D E F G H K L M N INCHES MIN MAX 0.750 0.785 0.240 0.295 --- 0.200 0.015 0.020 0.050 BSC 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 19.05 19.93 6.10 7.49 --- 5.08 0.39 0.50 1.27 BSC 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 0_ 15 _ 0.51 1.01
-T-
SEATING PLANE
N E F D G
16 PL
K M J
16 PL
0.25 (0.010)
M
M
TB
S
0.25 (0.010)
TA
S
-A-
16 9
P SUFFIX PLASTIC DIP PACKAGE CASE 648-08 ISSUE R
B
1 8
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01
F S
C
L
-T- H G D
16 PL
SEATING PLANE
K
J TA
M
M
0.25 (0.010)
M
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JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 03-81-3521-8315 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298
MOTOROLA 2-4
*MC10H016/D*
MC10H016/D MECL Data DL122 -- Rev 6

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